Intro to ASICs

Application-Specific Integrated Circuits (ASICs)

The ultimate expression of performance and efficiency is found in custom silicon. Application-Specific Integrated Circuits (ASICs) are the embodiment of this principle: integrated circuits designed for a particular rather than general-purpose functionality.1 Unlike a CPU that executes software instructions or an FPGA that can be reconfigured, an ASIC is a permanent, hardware-based implementation of a specific task. This singular focus allows them to deliver unparalleled performance at scale, making them the engines behind everything from smartphones to the core infrastructure of the internet.

A tray of application-specific integrated circuit (ASIC) chips Figure 1: A tray of application-specific integrated circuit (ASIC) chips

1. The Spectrum of Customisation

Creating an ASIC is not a one-size-fits-all process. The approach is tailored to the project's specific needs to balance performance, cost, and design time. The industry has settled on a few key design methodologies:

  1. Full-Custom Design: The most intensive approach, where engineers have control over the placement of every single transistor and the routing of every wire. This allows for the highest possible performance and the smallest chip area, which is critical for analog circuits and ultra-high-speed components. However, the design time and cost are immense, reserving this method for only the most demanding applications.2
  2. Standard-Cell Design: This is the workhorse of the modern digital ASIC industry. The design is built using a pre-characterised library of fundamental logic gates (like AND, OR, and flip-flops) called "standard cells." Sophisticated Electronic Design Automation (EDA) tools then automatically place these cells and route the connections between them. This approach offers a powerful compromise, enabling the creation of extremely complex chips with manageable design cycles.
  3. Gate-Array and Structured ASICs: In a gate-array approach, the silicon wafers are pre-fabricated with a generic sea of unconnected logic gates. The customisation occurs only in the final metal layers, which are designed to wire the gates together to create the desired circuit. This significantly reduces the non-recurring engineering (NRE) costs and manufacturing time.3 A modern evolution of this is the "structured ASIC," which pre-defines not just logic but also common, complex blocks like processors and memory, further speeding up the design cycle.

2. The Rise of the System-on-Chip (SoC)

As fabrication technology has advanced, it has become possible to integrate not just a single function but an entire system onto one piece of silicon. This is the concept of a System-on-Chip (SoC), and it is how virtually all modern ASICs are designed. An SoC can include multiple processor cores, memory blocks, graphics processing units, I/O controllers, and specialised accelerators.

The Power of IP Cores: Instead of designing every part of the SoC from scratch, engineers license pre-designed and pre-verified blocks of functionality known as Intellectual Property (IP) cores. Integrating a battle-tested Arm processor core or a standard USB interface can save a design team years of effort, reducing both risk and time-to-market.

These IP cores are the building blocks of modern SoCs and come in two main forms:

  • Soft Macros: These are flexible descriptions of a circuit in a Hardware Description Language (like Verilog or VHDL). They can be adapted and synthesised for different manufacturing processes.
  • Hard Macros: These are rigid, pre-laid-out designs that are optimised for a specific manufacturing process. They offer predictable performance and size but are less portable.

Microscope photograph of a gate-array ASIC showing the predefined logic cells and custom interconnections. This particular design uses less than 20% of available logic gates Figure 2: Microscope photograph of a gate-array ASIC showing the predefined logic cells and custom interconnections. This particular design uses less than 20% of available logic gates

3. From Concept to Silicon: The Design Flow

The journey to create an ASIC is a multi-stage process, enabled by an ecosystem of EDA tools and fabrication facilities (foundries). The typical digital design flow includes:

  1. RTL Design: The functionality of the chip is first described in a Hardware Description Language (HDL), creating a Register-Transfer Level (RTL) model.
  2. Functional Verification: This RTL description is rigorously tested through simulation to ensure it behaves as intended. This is a critical step, as flaws are vastly more expensive to fix after manufacturing.4
  3. Logic Synthesis: The HDL code is compiled into a gate-level "netlist," a detailed map of standard cells and the connections between them.
  4. Place and Route: The synthesis tool's output is then used to physically place the millions of standard cells onto the silicon floor plan and route the tiny metal wires to connect them all.
  5. Sign-off and Fabrication: The final layout is put through an exhaustive series of final checks (timing analysis, design rule checks). Once it passes "sign-off," the design is sent to a foundry to be fabricated, a process that can take several months.

This intricate process has enabled the creation of ASICs that power nearly every aspect of the digital world, from the custom chips in Apple iPhones and Google's Tensor Processing Units for AI to the networking ASICs that route traffic across the internet.

4. The Unwavering Trade-Off: ASIC vs. FPGA

For any new product, engineers face a decision: commit a design to a permanent ASIC or use a reconfigurable FPGA. The choice is a classic trade-off.5

  • Cost & Time-to-Market: FPGAs have zero non-recurring engineering (NRE) costs; you can buy one and program it in hours. An ASIC requires millions of dollars in NRE for the design effort and the photolithographic masks used in fabrication, and the design process can take years. FPGAs provide an unmatched advantage in speed to market.
  • Performance & Power: An ASIC will always be superior for a given task. Because it is custom-built, it can achieve higher speeds, greater processing throughput, and far lower power consumption than an FPGA implementation of the same logic.
  • Volume: This is the deciding factor. The high NRE of an ASIC must be amortised over the number of units sold. For prototypes and low-to-medium volume products, FPGAs are almost always more cost-effective. For mass-market products that will ship in the millions, the much lower per-unit cost of an ASIC makes it the only financially viable option.

In conclusion, while FPGAs offer invaluable flexibility, ASICs represent the commitment to creating a perfectly optimised solution. They are the bedrock of high-volume, high-performance electronics, turning years of design effort into the efficient, powerful, and cost-effective devices that shape our world.

Footnotes

  1. Golshan, K. (2007). Physical Design Essentials: An ASIC Design Implementation Perspective. Springer. ↩

  2. Smith, M. J. S. (1997). Application-Specific Integrated Circuits. Addison-Wesley Professional. ↩

  3. Barkalov, A., Titarenko, L., & Mazurkiewicz, M. (2019). Foundations of Embedded Systems. Springer International Publishing. ↩

  4. Hurley, J. M., & Carmen. (2019). Logic Design. EDTECH. ↩

  5. Kriegbaum, J. (2004, September 13). FPGA's vs. ASIC's. EE Times. ↩

By Kirk.